In the Linux kernel, the following vulnerability has been resolved: arm64: errata: Add Cortex-A520 speculative unprivileged load workaround Implement the workaround for ARM Cortex-A520 erratum 2966298. On an affected Cortex-A520 core, a speculatively executed unprivileged load might leak data from a privileged load via a cache side channel. The issue only exists for loads within a translation regime with the same translation (e.g. same ASID and VMID). Therefore, the issue only affects the return to EL0. The workaround is to execute a TLBI before returning to EL0 after all loads of privileged data. A non-shareable TLBI to any address is sufficient. The workaround isn't necessary if page table isolation (KPTI) is enabled, but for simplicity it will be. Page table isolation should normally be disabled for Cortex-A520 as it supports the CSV3 feature and the E0PD feature (used when KASLR is enabled).
| Métrique | Valeur | Interprétation |
|---|---|---|
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AV (Vecteur d'Attaque)
Attack Vector
|
Network (N)
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Exploit possible à distance via réseau (HTTP, API, etc.) |
|
AC (Complexité d'Attaque)
Attack Complexity
|
Low (L)
|
Peu de conditions requises pour exploiter |
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PR (Privilèges Requis)
Privileges Required
|
High (H)
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Authentifié avec privilèges administratifs |
|
UI (Interaction Utilisateur)
User Interaction
|
None (N)
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Aucune interaction utilisateur nécessaire |
|
S (Périmètre)
Scope
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Unchanged (U)
|
Impact reste dans le périmètre du composant compromis |
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C (Impact Confidentialité)
Confidentiality Impact
|
Low (L)
|
Divulgation limitée d'informations |
|
I (Impact Intégrité)
Integrity Impact
|
Low (L)
|
Modification limitée des données possible |
|
A (Impact Disponibilité)
Availability Impact
|
Low (L)
|
Interruption partielle du service possible |
arm64: errata: Add Cortex-A520 speculative unprivileged load workaround